Manufacturers of memory devices used in processing circuits and provided in graphics memory cards and users of such memory devices experience a continuous increase in demand for memory density and speed. The manufacturers and system on chip (SoC) vendors may respond by increasing the operating frequency of memory systems. For example, there is continuous pressure to increase the operating frequency of double data rate (DDR) synchronous dynamic random access memory (SDRAM). For example, the nominal operating frequency of fourth generation low-power DDR (LPDDR4) of 4.2 gigabits per second (Bbps) may be insufficient to meet evolving application demands. There is also continuous pressure on designers to decrease power consumption while maintaining or increasing data rates associated with memory devices used in mobile communication devices, for example, in order to decrease battery drain through reduced power consumption.
By way of example of high-speed memory, the JEDEC Solid State Technology Association, or the Joint Electron Device Engineering Council (JEDEC) has specified the graphics double data rate type 5 (GDDR5) standard to provide a high-speed interface for LPDDR4 and other highs speed memory devices and arrays, including graphics cards and the like. Memory devices conforming to the GDDR5 standard can transfer to 32-bit wide data words per write clock (WCK). In order to accomplish the specified throughput, a memory device may perform a 256 bit wide write or read access within two clock cycles at the internal memory core. Such memory device may transfer eight corresponding 32-bit wide words at the I/O pins over a series of half WCK clock cycles.
The use of a WCK clocking scheme to meet higher speeds may increase the number of pins required for I/O and the power consumed when toggling the WCK. In some implementations, jitter and phase offsets may be addressed using an error detection and correction (EDC) signal, and a data bus inversion signal that provides timing information can be used to control signaling related to a corresponding byte of data transmitted on the memory bus, thereby increasing the pin requirement and power consumption further.